The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that can operate at a low power by reducing power consumption of a toggling clock signal.
A semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) receives data from a source external to the device in response to an external clock signal, and outputs internal data to the outside in response to an internal clock signal. That is, the semiconductor memory device processes data using the internal clock signal, not the external clock signal, in the output mode. In other words, data input in synchronization with the external clock signal is output in synchronization with the internal clock signal. Such a change of clock signal from one to another is referred to as “domain crossing.”
A lot of circuits are included in the semiconductor memory device to allow the domain crossing. An output enable signal generator is a representative example. The output enable signal generator allows data transferred in synchronization with an internal clock signal to output in synchronization with an external clock signal after a column address strobe (CAS) latency.
A DDR product and a DDR2 product include a delay locked loop (DLL) for generating a DLL clock signal, and use the generated DLL clock signal to output data. However, a recently developed GDDR5 product, which are mostly used in a graphic memory, uses a clock signal, WCLK (hereinafter, referred to as ‘write/read clock signal’), instead of the DLL clock signal. For reference, the GDDR5 product receives an HCLK (hereinafter, referred to as ‘host clock signal’) and the write/read clock signal from an external device. The host clock signal is used in operations related to an external command, an address, and a core, and the write/read clock signal is used in both a read operation and a write operation of the semiconductor memory device. Generally, a frequency of the write/read clock signal is two times higher than that of the host clock signal. The write/read clock signal and the host clock signal are defined in the specification.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a frequency dividing circuit 110, a buffer circuit 130, an output enable signal generation circuit 150, and a data output circuit 170.
The frequency dividing circuit 110 divides a write/read clock signal WCLK to generate a data clock signal WCLK/2. In general, the frequency dividing circuit 110 divides the write/read clock signal WCLK in half to generate the data clock signal WCLK/2. For reference, the data clock signal WCLK/2 has the same frequency as a host clock signal HCLK.
The buffer circuit 130 buffers the data clock signal WCLK/2 to generate a read clock signal CLK_RD. The read clock signal CLK_RD has nearly the same frequency as the data clock signal WCLK/2.
The output enable signal generation circuit 150 receives a read command RD, a CAS latency CL, the host clock signal HCLK, and the data clock signal WCLK/2 to generate an output enable signal OE. The output enable signal generation circuit 150 synchronizes the read command RD to the data clock signal WCLK/2 to output the output enable signal OE according to the CAS latency CL. Here, the read command is generated by decoding an external command received from an external device, and is synchronized to the host clock signal HCLK. The CAS latency has information about a time for outputting data after receipt of the read command RD. The CAS latency is set by a mode register set. The output enable signal OE is synchronized to the data clock signal WCLK/2.
The data output circuit 170 receives an internal data DAT_IN to output an external data DAT_OUT in response to the output enable signal OE.
Circuits of the frequency dividing circuit 110, the buffer circuit 130, the output enable signal generation circuit 150, and the data output circuit 170 are well known to those skilled in the art. Therefore, detail circuits thereof will be omitted herein.
FIG. 2 is a timing diagram illustrating a read operation of the conventional semiconductor memory device of FIG. 1.
FIG. 2 shows waveforms of the data clock signal WCLK/2, the output enable signal OE, a read clock signal CLK_RD, a data control signal POUT_CL3, and the external data DAT_OUT. For reference, the data control signal POUT_CL3 is generated by the data output circuit 170.
As the read command RD is applied, the output enable signal OE is activated according to the CAS latency CL. In the embodiment, the output enable signal OE is activated at −4 clock from the CAS latency. This may be different according to a design of the semiconductor memory device. The read clock signal CLK_RD is a toggling clock signal. The output enable signal OE is synchronized to the read clock signal CLK_RD to generate a data control signal POUT_CL3. After the activation of the data control signal POUT_CL3, the internal data DAT_IN in FIG. 1 is output as an external data DAT_OUT in response to the read clock signal CLK_RD. Here, the data DATA is output 2 clocks after the activation of the data control signal POUT_CL3. This may also be different according to the design of the semiconductor memory device. Because a burst length is set to 8, eight data are output in response to the read clock signal CLK_RD.
Recently, the semiconductor memory device is designed to improve speed and reduce power consumption. To improve the speed, frequency of the toggling clock signal in the semiconductor memory device increases gradually. However, the clock signal toggling at high frequency increases power consumption. Especially, although the read clock signal CLK_RD is directly related to the data output, the read clock signal CLK_RD continuously toggles out of the period required to output data. In addition, because the read clock signal CLK_RD toggles during operations, such as a precharging operation, other than the read operation, extremely great power is consumed. As the number of data pads increases, the read clock signal CLK_RD is used more frequently. Therefore, the power consumption increases further.